The present invention relates to fixed information content memories often referred to as read-only memories (ROM) and, more particularly, to such memories which are subject to charge generating disturbances.
The structural features occurring in monolithic integrated circuit chips have been shrinking in size rapidly in recent years. With such shrinkage in feature sizes, electrical currents and electrical charge accumulations formed and manipulated in such integrated circuits have had to also diminish in value. In these circumstances, charge accumulation quantities generated by certain charge generating disturbances, which in integrated circuits with larger feature sizes would not be a problem, now become quantities that are sufficiently large to cause difficulties in integrated circuits with these smaller features.
Memory circuits typically operate by having a plurality of memory cells each of which is in one state or another as reflected in having some output at one or the other of two logic voltage levels. If these circuits are constructed using the smaller integrated circuit features currently available, the disturbance charges referred to can be sufficient to cause switching from an existing logic level to the opposite at points in the circuit where such charge is generated. Any such switching could lead to improper operation of the circuit resulting in erroneous logic signals from memory cells.
Typically, such disturbances are local to the region where the disturbance is generated and are temporary; thus, such a disturbance is often termed a "single event upset." Also, though the disturbance cause may be temporary, results of the disturbance may be stored and are subject to being propagated further in the system which may lead to a longer term and more significant effect.
A typical source of such charge generating disturbances is particle radiation. Such particles impinging on a monolithic integrated circuit will have "interactions" with the semiconductor material lattice structure and with electrons along its path through the integrated circuit semiconductor material. These interactions will result in raising the energy of the electrons involved into the conduction band and leave corresponding holes in the valence band. Should such electron-hole pairs be generated sufficiently close to a semiconductor pn junction, the electrons and holes so situated are subject to being collected by the action of electric fields in the region resulting because of voltage applied to such junction and because of diffusion toward such junction.
More wide spread charge disturbances which can occur over significant periods of time are termed "global ionization radiation" and may be caused by powerful electromagnetic radiation sources such as x-rays. Such global ionizing radiation will also generate electron-hole pairs which can also be collected by the action of electric fields in the region near a pn junction. The structure of transistor devices in monolithic integrated circuits, and the method of operating both such devices and the circuits using them generally, is such that only reverse-biased pn junctions need to be considered in determining the effects of such particle and electromagnetic wave radiation. For present purposes, these radiations can be considered as generating electron-hole pairs which lead to induced currents in the reverse current direction across affected pn junctions.
In the typical ROM memory circuit constructed of metal-oxide-semiconductor field-effect transistors (MOSFET's) there are four common device combination choices available in selecting and arranging these kinds of transistors to construct the circuit. The first of these is to use all p-channel transistor in a bit line column as word line controlled switching transistors with a p-channel transistor having its source connected to a positive voltage as a load or precharge transistor. Thus, there will be p-channel transistor sources connected to ground and drains connected to the bit line column which will be separated by reverse-biased pn junctions from the substrate. This construction in the presence of significant radiation will lead to a radiation induced current situation which can be modeled by providing a current generator in the memory circuit representing the generation of all these induced junction currents in total. This generator is connected between the substrate and the bit line column directed toward providing current to the bit line column. Thus, radiation will lead to currents which attempt to charge the bit line column. In substantial radiation situations, such currents could provide charge in such large quantities that the column p-channel switching transistors would be unable to sink sufficient current to cause the bit line column to drop in voltage toward ground potential upon a command on a word line connected to the gate of a column p-channel transistor to signify a change in state.
A voltage source interconnection variation for this device combination would be to have the load transistor connected to ground rather than to a positive voltage, and to have the controlled transistors connected to a positive voltage rather than ground. The bit line will be recharged to a low voltage level. The radiation induced current generator, with current directed to still flow into the bit line, again attempts to charge this line. If sufficient current on this line flows, the load transistor will be unable to set the bit line at a low voltage level with the result that voltage thereon will rise even though no word line command has switched on a word line controlled transistor.
Another possibility is the use of all n-channel transistors both as switching transistors connected between the column bit line and a positive voltage with the gates thereof driven by word lines, and as the load or precharge transistor for the column bit line which transistor is connected to ground. In this arrangement, radiation induced currents across the source and drain junctions can again be modeled by having a current generator connected between the bit line column and the substrate directing current into this substrate. Such a generator will have a current flow directed to always attempt to discharge the bit line column to lower the voltage thereon. This discharging by the current generator representing radiation induced currents can be sufficient to prevent the bit line column switching transistors under the command of a word line from being capable of raising the voltage on the bit line column to signify a state change.
A similar voltage source interconnection variation for this device combination is possible here also by instead connecting the lead transistor to a positive voltage and the word line controlled transistors to ground. The radiation induced generator in sinking current from the bit line in sufficient quantities could prevent the lead transistor from raising the voltage on the bit line to precharge it.
The remaining two device combination possibilities commonly encountered depend on complementary symmetry MOSFET's, i.e. CMOS, circuitry where the switching transistors along a bit line column are either all p-channel or n-channel transistors with the opposite transistor type serving as the load or precharge transistor. The results in these circuits are quite similar to the all p-channel and n-channel transistor cases described above. That is, the circuits can be modeled by having a current generator representing the total of the radiation induced currents connected between the bit line column and the substrate. Such generators always provide currents in a direction which lead to the switching transistors connected to the bit line column being unable to drive the voltage on the bit line column to the level desired upon command signals being provided on the word lines connected to the switching transistor gates. The desired level may be either a higher or low level depending on the voltage supply interconnections and the selected device combination.
The situation will be somewhat better in such CMOS circuitry, however, than in that circuitry described in the foregoing with just one kind of MOSFET. This is because the switching transistors, being just one kind of MOSFET, can be contained in an isolating region to electrically isolate them from transistors of the other type. Such a structure reduces the amount of charge collected at the junctions separating these transistor drains from the isolating region because about half the charge generated will be swept across the reverse-biased isolating region substrate pn junction. Thus, lesser valued current generators can be used between the bit line column and the isolating region to represent the radiation induced currents. Nevertheless, this arrangement can have other difficulties such as slow switching.
Thus, there is a need for a ROM memory structure which will be less subject to improper operation in an environment of particle or electromagnetic wave radiation. Such a structure should also permit rapid switching of the switching devices connected to the bit line columns therein, and be compatible with a sensing arrangement also constructed to avoid improper operation of the memory in this kind of an environment.